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features ? 16 mbit sram multi chip module ? allows 32-, 16- or 8-bit access configuration ? operating voltage: 3.3v + 0.3v ? access time ? 20 ns, 18 ns for AT68166F ? <18 ns for at68166g (in development prototypes in q4 2007) ? power consumption ? active: 620 mw per byte (max) @ 18ns - 415 mw per byte (max) @ 50ns (1) ? standby: 13 mw (typ) ? military temperature range: -55 to +125 c ? ttl-compatible inputs and outputs ? asynchronous ? die manufactured on atmel 0.25 m radiation hardene d process ? no single event latch up below let threshold of 80 mev/mg/cm 2 ? tested up to a total dose of 300 krads (si) accordi ng to mil-std-883 method 1019 ? esd better than 4000v ? quality grades: ? qml-q or v with smd 5962-06229 ? escc ? 950 mils wide mqfp 68 package ? mass : 8.5 grams note: 1. only for AT68166F-18. 450mw for AT68166F-20. description the AT68166F/g is a 16mbit sram packaged in a herme tic multi chip module (mcm) for space applications. the AT68166F/g mcm incorporates four 4mbit at60142f t sram dice. it can be organized as either one bank of 512kx8, two banks o f 512kx16 or four banks of 512kx8. it combines rad-hard capabilities, a latch- up threshold of 80mev.cm2/mg, a multiple bit upset immunity and a total dose tolera nce of 300krads, with a fast access time. the mcm packaging technology allows a reduction of the pcb area by 50% with a weight savings of 75% compared to four 4mbit packag es. thanks to the small size of the 4mbit sram die, atm el has been able to accommo- date the assembly of the four dice on one side of t he package which facilitates the power dissipation. the compatibility with other products allows design ers to easily migrate to the atmel AT68166F/g memory. the AT68166F/g is powered at 3.3v. the AT68166F/g is processed according to the test m ethods of the latest revision of the mil-prf-38535 or the escc 9000. 7747a?aero?07/07 rad hard 16 megabit 3.3v sram multi- chip module AT68166F at68166g
2 7747a?aero?07/07 AT68166F/g block diagram figure 1. AT68166F/g block diagram figure 2. 512k x 8 banks block diagram (at60142f/g) packages AT68166F and at68166g are packed in mqfp68. the pin assignment depends on the access time. ther e are 2 versions: ? ym package where 3 pins are not connected. ? ys package where the 3 above pins are connected to gnd or v cc . a[18:0] oe cs1 we1 i/o[15:8] bank1 512k x 8 cs2 we2 i/o[23:16] bank2 512k x 8 cs3 we3 i/o[31:24] bank3 512k x 8 cs0 we0 i/o[7:0] bank0 512k x 8 or i/o2[31:16] or i/o2[15:0] or i/o1[31:16] or i/o1[15:0] or i/o3[7:0] or i/o2[7:0] or i/o1[7:0] or i/o[7:0] a 0 -- - a 10 i/ox 0 i/ox 7 cs x we x oe access time 20 ns 18 ns <18 ns AT68166F ym ys at68166g ys
3 7747a?aero?07/07 AT68166F/g pin configuration table 1. AT68166F/g pin assignment in ys package notes: 1. in ym package leads 33, 34 and 68 are not c onnected. lead signal lead signal lead signal lead signal 1 i/o0[0] 18 vcc 35 i/o3[7] 52 vcc 2 i/o0[1] 19 a11 36 i/o3[6] 53 a10 3 i/o0[2] 20 a12 37 i/o3[5] 54 a9 4 i/o0[3] 21 a13 38 i/o3[4] 55 a8 5 i/o0[4] 22 a14 39 i/o3[3] 56 a7 6 i/o0[5] 23 a15 40 i/o3[2] 57 a6 7 i/o0[6] 24 a16 41 i/o3[1] 58 we0 8 i/o0[7] 25 cs0 42 i/o3[0] 59 cs3 9 gnd 26 oe 43 gnd 60 gnd 10 i/o1[0] 27 cs1 44 i/o2[7] 61 cs2 11 i/o1[1] 28 a17 45 i/o2[6] 62 a5 12 i/o1[2] 29 we1 46 i/o2[5] 63 a4 13 i/o1[3] 30 we2 47 i/o2[4] 64 a3 14 i/o1[4] 31 we3 48 i/o2[3] 65 a2 15 i/o1[5] 32 a18 49 i/o2[2] 66 a1 16 i/o1[6] 33 gnd 50 i/o2[1] 67 a0 17 i/o1[7] 34 vcc 51 i/o2[0] 68 vcc
4 7747a?aero?07/07 AT68166F/g figure 3. AT68166F pin assignment in ym package figure 4. AT68166F/g pin assignment in ys package i/o0[0] i/o0[1] i/o0[2] i/o0[3] i/o0[4] i/o0[5] i/o0[6] i/o0[7] gnd i/o1[0] i/o1[1] i/o1[2] i/o1[3] i/o1[4] i/o1[5] i/o1[6] i/o1[7] i/o2[0] i/o2[1] i/o2[2] i/o2[3] i/o2[4] i/o2[5] i/o2[6] i/o2[7] gnd i/o3[0] i/o3[1] i/o3[2] i/o3[3] i/o3[4] i/o3[5] i/o3[6] i/o3[7] AT68166F (top view) nc a0 a1 a2 a3 a4 a5 cs2 gnd cs3 we0 a6 a7 a8 a9 a10 vcc nc nc a18 we3 we2 we1 a17 cs1 0e cs0 a16 a15 a14 a13 a12 a11 vcc 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 i/o0[0] i/o0[1] i/o0[2] i/o0[3] i/o0[4] i/o0[5] i/o0[6] i/o0[7] gnd i/o1[0] i/o1[1] i/o1[2] i/o1[3] i/o1[4] i/o1[5] i/o1[6] i/o1[7] i/o2[0] i/o2[1] i/o2[2] i/o2[3] i/o2[4] i/o2[5] i/o2[6] i/o2[7] gnd i/o3[0] i/o3[1] i/o3[2] i/o3[3] i/o3[4] i/o3[5] i/o3[6] i/o3[7] AT68166F/g (top view) vcc a0 a1 a2 a3 a4 a5 cs2 gnd cs3 we0 a6 a7 a8 a9 a10 vcc vcc gnd a18 we3 we2 we1 a17 cs1 0e cs0 a16 a15 a14 a13 a12 a11 vcc 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
5 7747a?aero?07/07 AT68166F/g pin description table 2. pin names note: 1. the package lid is connected to gnd table 3. truth table (1) name description a0 - a18 address inputs i/o0 - i/o31 data input/output cs0 - cs3 chip select w e 0 - we3 write enable oe output enable vcc power supply gnd (1) ground cs x w e x oe inputs/outputs mode h x x z standby l h l data out read l l x data in write l h h z output disable note: 1. l=low, h=high, x= h or l, l=high impedance.
6 7747a?aero?07/07 AT68166F/g electrical characteristics absolute maximum ratings* military operating range recommended dc operating conditions capacitance note: 1. guaranteed but not tested. supply voltage to gnd potential:................... ......-0.5v + 4.6v dc input voltage:.................................. ......gnd -0.5v to 4.6v dc output voltage high z state: ................gnd -0.5v to 4.6v storage temperature: ............................... .... -65 c to + 150 c output current into outputs (low): ................. .............. 20 ma electro statics discharge voltage:..... .........> 4 000v (mil std 883d method 3015.3) *note: stresses beyond those listed under "absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and functional oper- ation of the device at these or any other condition s beyond those indicated in the operational sections of this specification is not implied. exposure to abso lute maximum rating conditions for extended periods may affect device reliability. operating voltage operating temperature 3.3 + 0.3v -55 c to + 125 c parameter description min typ max unit vcc supply voltage 3 3.3 3.6 v gnd ground 0.0 0.0 0.0 v v il input low voltage gnd - 0.3 0.0 0.8 v v ih input high voltage 2.2 ? v cc + 0.3 v parameter description min typ max unit c in (1) (oe and ax) input capacitance ? ? 48 pf c in (1) (csx and wex) input capacitance ? ? 12 pf c io (1) i/o capacitance ? ? 12 pf
7 7747a?aero?07/07 AT68166F/g dc parameters notes: 1. gnd < v in < v cc , gnd < v out < v cc output disabled. 2. v cc min. i ol = 8 ma 3. v cc min. i oh = -4 ma consumption notes: 1. all csx > v ih 2. all csx > v cc - 0.3v 3. f = 1/ tavav , i out = 0 ma, wex = oe = v ih , v in = gnd/v cc , v cc max. 4. f = 1/ tavaw , i out = 0 ma, we x = v il , oe = v ih , v in = gnd/v cc , v cc max. parameter description minimum typical maximum unit iix (1) input leakage current -1 ? 1 a ioz (1) output leakage current -1 ? 1 a vol (2) output low voltage ? ? 0.4 v voh (3) output high voltage 2.4 ? ? v symbol description tavav/tavaw test condition AT68166F-20 AT68166F-18 unit value i ccsb (1) standby supply current ? 10 7 ma max i ccsb1 (2) standby supply current ? 8 6 ma max i ccop (3) read per byte dynamic operating current 18 ns 20 ns 50 ns 1 s ? 170 85 15 170 165 80 12 ma max i ccop (4) write per byte dynamic operating current 18 ns 20 ns 50 ns 1 s ? 150 125 110 145 140 115 105 ma max
8 7747a?aero?07/07 AT68166F/g data retention mode atmel cmos ram's are designed with battery backup i n mind. data retention voltage and sup- ply current are guaranteed over temperature. the fo llowing rules insure data retention: 1. during data retention chip select csx must be held high within v cc to v cc -0.2v. 2. output enable (oe ) should be held high to keep the ram outputs high impedance, mini- mizing power dissipation. 3. during power-up and power-down transitions csx and oe must be kept between v cc + 0.3v and 70% of v cc . 4. the ram can begin operation > t r ns after v cc reaches the minimum operation voltages (3v). figure 5. data retention timing data retention characteristics vcc csx parameter description min typ t a = 25 c max unit v ccdr v cc for data retention 2.0 ? ? v t cdr chip deselect to data retention time 0.0 ? ? ns t r operation recovery time t avav (1) 1. t avav = read cycle time. ? ? ns i ccdr (2) 2. all csx = v cc , v in = gnd/v cc . data retention current ? 3 6 (AT68166F-20) ma 4.5 (AT68166F-18)
9 7747a?aero?07/07 AT68166F/g ac characteristics temperature range:................................. ............... -55 +125 c supply voltage: .................................... ................... 3.3 + 0.3v input pulse levels: ................................ .................. gnd to 3.0v input rise and fall times:......................... .............. 3ns (10 - 90%) input and output timing reference levels: .......... .. 1.5v output loading i ol /i oh :............................................ see fi gure 3 figure 6. ac test loads waveforms write cycle table 4. write cycle timings (1) notes: 1. timings figures applicable for 8-bit, 16-bi t and 32-bit mode. 2. parameters guaranteed, not tested, with output lo ading 5 pf. (see ?ac test loads waveforms? on page 9.) specific (twlqz, twhqx, telqx, tehqz tglqx, tghqz) general symbol parameter AT68166F-20 AT68166F-18 unit min max min max tavaw write cycle time 20 - 18 - ns tavwl address set-up time 2 - 2 - ns tavwh address valid to end of write 14 - 11 - ns tdvwh data set-up time 9 - 8 - ns telwh cs low to write end 12 - 12 - ns twlqz write low to high z (2) - 10 - 8 ns twlwh write pulse width 12 - 9 - ns twhax address hold from end of write 0 - 0 - ns twhdx data hold time 2 - 1 - ns twhqx write high to low z (2) 5 - 3 - ns
10 7747a?aero?07/07 AT68166F/g figure 7. write cycle 1. w e controlled, oe high during write figure 8. write cycle 2. w e controlled, oe low figure 9. write cycle 3. cs controlled the internal write time of the memory is defined by the overlap of cs low and we low. both signals must be activated to initiate a write and either signal can terminate a write by going in active mode. the data input setup and hold timing should be referenced to the active edge of the signal that terminates the write. data out is high impedance if oe = v ih . e e address csx wex i/os oe e e address csx wex i/os e address csx wex i/os
11 7747a?aero?07/07 AT68166F/g read cycle table 5. read cycle timings (1) notes: 1. timings figures applicable for 8-bit, 16-bi t and 32-bit mode. 2. parameters guaranteed, not tested, with output lo ading 5 pf. (see ?ac test loads waveforms? on page 9.) figure 10. read cycle nb 1: address controlled (cs = oe = v il , we = v ih ) symbol parameter AT68166F-20 AT68166F-18 unit min max min max tavav read cycle time 20 - 18 - ns tavqv address access time - 20 - 18 ns tavqx address valid to low z 5 - 5 - ns telqv chip-select access time - 20 - 18 ns telqx cs low to low z (2) 5 - 5 - ns tehqz cs high to high z (2) - 9 - 8 ns tglqv output enable access time - 11 - 8 ns tglqx oe low to low z (2) 2 - 2 - ns tghqz oe high to high z (2) - 9 - 8 ns address dout
12 7747a?aero?07/07 AT68166F/g figure 11. read cycle nb 2: chip select controlled (we = v ih ) csx oe dout
13 7747a?aero?07/07 AT68166F/g typical applications this section presents some standard implementations of the AT68166F/g in application. 32-bit mode application when used on a 32-bit (word) application, the modul e shall be connected as follow : ? the 32 lines of data are connected to distinct dat a lines ? the four csx are connected together and linked to a single host cs output ? each one of the four we x is connected to a dedicated we line on the host to allow byte, half word and word format write. figure 12. 32-bit typical application ( 1 sram bank) 16-bit mode application when used on a 16-bit (half word) application, the module can be connected as presented in the following figure. this allows use of a single at681 66f/g part for two sram memory banks. all input controls of the AT68166F/g not used in th e application shall be pulled-up. figure 13. 16-bit typical application (two sram banks) 8-bit mode application when used on a 8-bit (byte) application, the module can be connected as presented in the fol- lowing figure. this allows use of a single AT68166F /g part for up to four sram memory banks. all input controls of the AT68166F/g not used in th e application shall be pulled-up. cs [3:0] oe we [3:0] a[17:0] i/o[31:0] AT68166F/g ramoe0* a d at697e a[27:0] d[31:0] d[31:0] a[19:2] rwe[3:0]* rams0* a[19:2] d[31:0] a[17:0] i/o[15:0] AT68166F/g a d at697e a[27:0] d[31:0] d[31:16] a[18:1] a[18:1] d[31:0] i/o[31:16] d[31:16] cs [1:0] we [1:0] rwe0* rams0* cs [3:2] we [3:2] rwe0* rams1* oe ramoe[1:0]*
14 7747a?aero?07/07 AT68166F/g figure 14. 8-bit typical application (two sram banks) a[17:0] i/o[7:0] AT68166F/g a d at697e a[27:0] d[31:0] d[31:24] a[17:0] a[17:0] d[31:0] i/o[15:8] d[31:24] cs [0] we [0] rwe0* rams0* cs [1] we [1] rwe0* rams1* oe ramoe[1:0]* cs [3] we [3] rwe0* rams2* cs [2] we [2] rwe0* rams2* i/o[23:16] d[31:24] i/o[31:24] d[31:24]
15 7747a?aero?07/07 AT68166F/g ordering information note: 1. will be replaced by smd part number when ava ilable. part number temperature range speed package flow AT68166F AT68166F-ym20-e 25 c 20 ns mqfp68 engineering samples 5962-0622902qxc -55 to +125 c 20 ns mqfp68 qml q 5962-0622902vxc -55 to +125 c 20 ns mqfp68 qml v 5962r0622902vxc -55 to +125 c 20 ns mqfp68 qml v rha AT68166F-ym20-scc -55 to +125 c 20 ns mqfp68 escc AT68166F-ys18-e 25 c 18 ns mqfp68 engineering samples AT68166F-ys18-mq (1) -55 to +125 c 18 ns mqfp68 qml q AT68166F-ys18-sv (1) -55 to +125 c 18 ns mqfp68 qml v AT68166F-ys18-sr (1) -55 to +125 c 18 ns mqfp68 qml v rha AT68166F-ys18-scc (1) -55 to +125 c 18 ns mqfp68 escc
16 7747a?aero?07/07 AT68166F/g package drawings 68-lead quad flat pack (950 mils) with non conducti ve tie bar note: lid is connected to ground. note: ym and ys package drawings are identical.
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